The present invention relates generally to the fabrication of silicon gate structures and more specifically to a method for using in-situ photoresist trim, gate etch, and high-k dielectric removal along with small-wavelength photolithography to fabricate a transistor gate of a dimension below that which could be achieved by small-wavelength photolithography alone, thus enabling creation of a higher density gate array on a silicon integrated circuit (IC).
Silicon-based integrated circuits often utilize a field effect transistor (FET) structure that comprises a polysilicon gate positioned over a channel region within a silicon wafer, with a dielectric layer insulating the polysilicon gate from the channel region over which the polysilicon gate is positioned.
As is well-known to those of ordinary skill in the relevant art, a photolithographic process is commonly used to fabricate the polysilicon gate. This process involves making a laminate structure, and then selectively removing portions of that laminate to create the desired structure, which in this case is a gate. The laminate structure typically comprises a substantially planar silicon wafer substrate. Upon this substrate are deposited an oxide layer; upon the oxide layer is deposited a polysilicon layer; upon the polysilicon layer is deposited an anti-reflective coating (ARC) layer; upon the anti-reflective coating (ARC) layer is deposited a photoresist layer. A reticle containing pattern representing the desired structure is positioned between an illumination source and the photoresist layer, such that the photoresist is patterned. Next, the photoresist is developed so as to mask the polysilicon gate. An anisotropic etch is then used to remove the un-masked polysilicon such that the polysilicon gate is formed.
Ordinarily, the size of the structure (e.g., a gate) ultimately fabricated corresponds to the size of the photoresist structures deposited during the photolithographic process. That size, in turn, is dependent on wavelength, such that smaller sizes are generally produced by (and therefore generally require) smaller wavelengths.
Since, generally speaking, gate size reduction leads to increased performance, it is a generally recognized goal to decrease the size of the polysilicon gate. First, decreasing the gate size permits decreasing the size of each individual silicon device. Decreasing the size of each device provides the ability to increase the density of a device array fabricated on a wafer which provides the ability to fabricate a more complex circuit with a faster operating speed on a wafer of a given size. Secondly, a smaller channel region beneath a smaller gate reduces capacitance across the channel/source junction and the channel drain junction which provides for faster operating speed and reduced power consumption.
However, it is difficult to reduce gate size. Ordinarily, limitations on the masking and etching processes limit gate size. For example, the resolution of the photoresist masking processes provides a lower limit on the minimum gate size. For other reasons, etching processes for etching vertical surfaces perpendicular to the horizontal mask further limit the minimum gate size due to erosion and other effects that degrade the etch profile.
One caveat remains: while reducing gate size is generally desirable, there does exist a minimum physical thickness of the gate oxide below which the oxide no longer insulates the gate from the channel region. To avoid this limitation, the gate may be formed from dielectrics with dielectric constants greater than silicon dioxide (e.g. high-k dielectrics), rather than the convention gate material, i.e. silicon dioxide, may be used to replace the conventional gate oxide to improve capacitive coupling. Advantageously, the use of high-k dielectric also provides improved capacitive coupling between the gate and the channel region, so as to provide the improved capacitive coupling required by a smaller gate size. However, high-k dielectric gate material reacts to various etching chemistries differently than does the usual dielectric gate material (silicon dioxide) and therefore the use of a high-k gate dielectric requires different fabrication methods than a similar structure with a conventional gate oxide.
Accordingly there is a strong need in the art for a narrow gate transistor structure that includes a high-k gate dielectric material and a method of forming same. It is preferable that such method provide for patterning a hard mask using short wavelength lithography to minimize feature size and provide for resist trimming to further reduce feature size. Preferably such method provides for in-situ resist trimming, hard mask formation, gate etch, and dielectric etch.
The present invention provides an efficient method of small geometry gate formation on the surface of a high-k gate dielectric. The method provides for processing steps that include photoresist mask trimming, hard mask formation, gate stack etching, and the removal of exposed regions of the high-k dielectric to be performed efficiently in a single etch chamber. Such method of performing in-situ resist trim, hard mask formation, gate etch, and high-k gate dielectric removal provides for a simplified process over known fabrication methods along with improving throughput. The method also reduces wafer handling and opportunities for contamination. The method comprises fabricating a gate dielectric etch stop layer above a silicon substrate. The gate dielectric etch stop layer comprising a material that has a dielectric constant greater than the dielectric constant of silicon dioxide and forms the gate dielectric in a region of the wafer that becomes the gate and forms a barrier to prevent polysilicon etching chemistries from damaging the silicon substrate in regions along side the gate. The method further comprises sequentially: a) fabricating a polysilicon layer above the gate dielectric etch stop layer; b) fabricating a hard mask layer above the polysilicon layer; and c) fabricating a photoresist layer over the hard mask layer. The photoresist layer is then patterned and developed to form a photoresist mask over a gate region and to expose an erosion region about and outside the periphery of the gate region.
The wafer is placed in an enclosed etching environment with high density plasma and, optionally an inert gas. The inert gas may be argon. While in such an etching environment the following etch processes are in-situ performed. First, a portion of the photoresist mask is etched to form a trimmed photoresist mask over a narrow gate region and to increase the size of the erosion region using an etch chemistry selective between the photoresist and the hard mask layer. The trimmed photoresist mask dimension is smaller the capability of either 248 nm or 193 nm lithography. Secondly, the hard mask layer is etched to form a hard mask over the narrow gate region and to expose the polysilicon in the erosion region. The polysilicon layer is then etched using an etch chemistry selective between the polysilicon and each of the hard mask and the gate dielectric etch stop layer. The gate dielectric etch stop layer is removed using an etch chemistry selective between the gate dielectric etch stop layer and both the polysilicon and the hard mask. And, finally, the hard mask is removed using wet etch.
The gate dielectric etch stop layer may comprise a high-k material selected from the group of HfO2, ZrO2, CeO2, Al2O3, TiO2, Y2O3. Within the environment, the step of trimming or etching a portion of the photoresist mask may comprise use of at least one of HBr, CL2, N2, He and O2 and the step of forming the hard mask may comprise etching the hard mask coating using CF4 or CHF3. The step of etching the polysilicon layer may comprise use of HBr, Cl2, CF4, and HeO2 (which is not truly a compound but industry shorthand for a combination of Oxygen diluted with a large amount of Helium provided to the etch chamber through a single mass flow controller), in a bias field to improve a vertical side profile between the gate region and the erosion region of the polysilicon. The HeO2 increases the selectivity between the polysilicon and the gate dielectric etch stop layer. Other etch parameters may also be used to improve the selectivity between the polysilicon and the gate dielectric etch stop layer. The step of removing the gate dielectric etch stop layer comprises use of HBr and He with the addition of Fluorine (F) gas. Alternatively. The step may comprise use of O2 and an inert gas with the addition of Fluorine gas.
For a better understanding of the present invention, together with other and further aspects thereof, reference is made to the following description, taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.